The present invention relates to a programmable memory circuit and, more particularly, to a complementary type programmable memory circuit which accesses selected one of a plurality of non-volatile semiconductor memory cells.
Since read and write voltages for the programmable memory have different levels, it is necessary to provide a circuit which can deal with voltages of two levels and control the supply of the two-level voltages to the memory. Conventionally, such a circuit is very complicated.
In order to decrease power consumption, it has been proposed to use complementary insulated gate field effect transistors (CMOSFETs) for a circuit adapted to access non-volatile semiconductor memory cells. However, many insulated gate field effect transistors (hereinafter referred to as IGFETs) must be used to constitute a multi-input circuit such as a decoder of the complementary IGFET type, and this circuit is not suited for high speed operations.